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atmel AT88SC0104CA atmel cryptomemory summary datasheet features ? one of a family of devices with user memories from 1 kbit to 8 kbits ? 1 kbit (128 - byte) eeprom user memory ? four 256 - bit (32 - byte) zones ? self - timed write cycle ? single byte or 16 - byte page write m ode ? programmable access rights for each zone ? 2 kbit configuration zone ? 37- byte otp area for user - defined codes ? 160- byte area for user - defined keys and passwords ? high security features ? 64- bit mutual authentication protocol ( under license of elva) ? cryptograph ic message authentication codes (mac) ? stream encryption ? four key sets for authentication and encryption ? eight sets of two 24 - bit passwords ? anti - tearing function ? voltage and frequency monitors ? smart card features ? iso 7816 class b (3v) operation ? iso 7816 -3 a synchronous t=0 protocol (gemplus ? patent) * ? multiple zones, key sets and passwords for multi - application use ? synchronous two - wire serial interface for faster device initializati on * ? programmable 8 -by te answer -to - reset register ? iso 7816 -2 compliant modules ? embedded application features ? low voltage supply : 2.7v ? 3.6v ? secure nonvolatile storage for sensitive system or user information ? two - wire serial interface (twi, 5v compatible ) ? 1.0 mhz compatibility for fast operation ? standard 8 - lead plastic packages, gree n compliant (exceeds rohs) ? same pin configuration a s atmel ? at24cxxx serial eeprom in soic and pdip packages ? high reliability ? endurance: 100,000 cycles ? data retention : 10 years ? esd protection : 2,000v min * note : modules available with either t = 0 / 2 - wir e modes or 2 - wire mode only 5200fs ? crypto ? 12 /11 this is a summary document. the complete docum ent is available on the atmel website at www.atmel.com.
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 2 table 1. pin assignments pad description iso module twi module ?soic, pdip? tssop mini - map v cc supply voltage c1 c1 8 8 4 gnd ground c5 c5 4 1 5 scl/clk serial clock input c3 c3 6 6 2 sda/io serial data input/output c7 c7 5 3 7 rst reset input c2 nc nc nc nc figure 1. pin configuration 1 2 3 4 8 7 6 5 8-lead soic, pdip nc nc nc gnd v cc nc scl sd a 8-lead tssop nc v cc 8 1 nc c n 7 2 nc k l c 6 3 gnd 5 4 s d a 1 2 3 4 8 7 6 5 s d a gnd clk v cc 8-lead ult r a thin mini-map (mlp 2x3) bo t t om v iew nc nc nc nc tw i smart card module v cc =c1 nc =c2 scl/clk=c3 nc=c4 c5=gnd c6=nc c7=s d a/io c8=nc iso smart card module v cc =c1 rst=c2 scl/clk=c3 nc=c4 c5=gnd c6=nc c7=s d a/io c8=nc
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 3 1. description the atmel AT88SC0104CA member of the atmel cryptomemory ? family is a high - perfor mance secure memory providing 1 kbit of user memory with advanced security and cryptographic features built in. the user memory is divided into four 32 - byte zones, each of which may be individually set with different security access rights or effectively combined together to provid e space for o ne to four data files. the AT88SC0104CA features an enhanced command set that allows direct communication with microcontroller hardware two - w ire interface thereby allowing for faster firmware development with reduced code space requirements. 1.1 smart card app lications the AT88SC0104CA provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. the embedded cryptographic engine provides for dynamic, symmetric - mutual authentication between the device and h ost, as well as performing stream encryption for all data and passwords exchanged between the device and host. up to four unique key sets may be used for these operations. the AT88SC0104CA offers the ability to communicate with virtually any smart card rea der using the asynchronous t = 0 protocol (gemplus patent) defined in iso 7816 - 3. 1.2 embedded applications through dynamic, symmetric - mutual authentication, data encryption, and the use of cryptographic message authentication codes (mac), the AT88SC0104CA pr ovides a secure place for storage of sensitive information within a system. with its tamper detection circuits, this information rem ains safe even under attack. a two - wire serial interf ace running at speeds up to 1.0 mhz provides fast and efficient communic ations with up to 15 individually addressable devices. the AT88SC0104CA is available in industry standard 8 - lead packages with the same familiar pin configuration as at24cxxx s erial eeprom devices. note: does not apply to either the tssop or the ultra thin mini - map pinouts figure 1 -1. block diagram random generator authentication, encryption and certification unit eeprom answer to reset data transfer password verification reset block asynchronous iso interface synchronous interface power management v cc gnd scl/clk s d a/io rst
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 4 2. connection diagram figure 2 -1. connection diagram 2.7v - 5.5v 2.7v - 3.6v sd a scl microprocessor cryptomemory 3. pin descriptions 3.1 supply voltage (v cc ) the v cc input is a 2.7v to 3.6v positive voltage supplied by the host. 3.2 clock (scl/clk) when using the asynchronous t = 0 protocol, the clk (scl) inp ut provides the device with a carrier frequency f . the nominal length of one bit emitted on i/o is defined as an ?elementary time unit? (etu) and is equal to 372/ f . when using the synchronous protocol, data clocking is done on the positive edge of the cl ock when writing to the device and on the negative edge of the clock when reading from the device. 3.3 reset (rst) the AT88SC0104CA provides an iso 7816 - 3 compliant asynchronous answer -to - reset (atr) sequence. upon activation of the reset sequence, the device outputs bytes contained in the 64 - bit answer -to - reset register. an internal pull - up on the rst input pad allows the device to operate in synchronous mode without bonding rst. the AT88SC0104CA does not support an answer -to - reset sequence in the synchronous mode of operation. 3.4 serial data (sda/io) the sda/io pin is bidirectional for serial data transfer. this pin is open - drain driven and may be wired with any number of other open - drain or open - collector devices. an external pull - up resistor should be connect ed between sda/io and v cc . the value of this resistor and the system capacitance loading the sda/io bus will determine the rise time of sda/io. this rise ti me will determine the maximum frequency during read operations. low value pull - up resistors will all ow higher frequency operations while drawing higher average power supply current. sda/io information applies to both asynchronous and synchronous protocols.
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 5 4. * absolute maximum ratings operating temperature .................... ? 40c to +85c storage temperature ................... ? 65c to + 150c voltage on any pin with respect to ground ............... ? 0.7 to v cc + 0.7 v maximu m operating voltage ............................. 4 .0v dc output current ......................................... 5.0ma * notice : stresses beyond those listed under ?absolute maximum ratings? may cause per manent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating co nditions for extended periods of time may affect device reliability . table 4 -1. dc characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c (unless otherwise noted) symbol parameter test conditions min typ max units v cc (1) supply voltage 2.7 3.6 v i cc supply current async read at 3.57mhz 5 ma i cc supply current async write at 3.57mhz 5 ma i cc supply current synch read at 1mhz 5 ma i cc supply current synch write at 1mhz 5 ma i sb standby current v in = v c c or gnd 100 a v il sda/io input low voltage 0 v cc x 0.2 v v il clk input low voltage 0 v cc x 0.2 v v il rst input low voltage 0 v cc x 0.2 v v ih (1) sda/io input high voltage v cc x 0.7 5.5 v v ih (1) scl/clk input high voltage v cc x 0.7 5.5 v v ih (1) rst input high voltage v cc x 0.7 5.5 v i il sda/io input low current 0 < v il < v cc x 0.15 15 a i il scl/clk input low current 0 < v il < v cc x 0.15 15 a i il rst input low current 0 < v il < v cc x 0.15 50 a i ih sda/io input high current v c c x 0.7 < v ih < v cc 20 a i ih scl/clk input high current v cc x 0.7 < v ih < v cc 100 a i ih rst input high current v cc x 0.7 < v ih < v cc 150 a v oh sda/io output high voltage 20k ohm external pull - up v cc x 0.7 v cc v v ol sda/io output low voltage i ol = 1ma 0 v cc x 0.15 v i oh sda/io output high current v oh 20 a i ol sda/io output low current v ol 10 ma note: 1. to prevent latch up conditions from occurring during power up o f the atmel AT88SC0104CA, v cc must be turned on before applying v ih . for powe ring down , v ih must be removed before turning v cc off
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 6 table 4 -2. ac characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c, cl = 30pf (unless otherwise noted) symbol parameter min max units f clk async clock fre quency 1 4 mhz f clk synch clock frequency 0 1 mhz clock duty cycle 40 60 % t r ?rise time - sda/io, rst? 1 s t f ?fall time - sda/io, rst? 1 s t r rise time - scl/clk 9% x period s t f fall time - scl/clk 9% x period s t aa clock low to data out valid 250 ns t hd.sta start hold time 200 ns t su.sta start set - up time 200 ns t hd.dat data in hold time 10 ns t su.dat data in set - up time 100 ns t su.sto stop set - up time 200 ns t dh data out hold time 20 ns t wr write cycle time 5 ms 5. device operations for synchronous protocols 5.1 clock and data transitions the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 5 - 3 on pa ge 8 ). data changes during scl high periods will indicate a start or stop condition as defined below. 5.1.1 start condition a high -to - low transition of sda with scl high defines a start condition which must precede all commands (see figure 5 -4 on page 8 ). 5.1.2 stop condition a low -to - high transition of sda with scl high defines a stop condition. after a read sequence, the stop condition will place the eeprom in a s tandby power mode (see figure 5 -4 on page 8 ). 5.1.3 acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the eeprom sends a zero to ack nowledge that it has received each word. this happens during the ninth clock cycle (see figure 5 -5 on page 8 ).
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 7 5.2 memory reset after an interruption in communication due protocol error s, power loss or any reason, perform "acknowledge polling" to properly recover from the condition. acknowledge polling consists of sending a start condition followed by a valid cryptomemory command byte and determining if the device responded with an ackno wledge . figure 5 -1. b us time for two - w ire serial communications scl: serial clock, sda: serial data i/o scl sd a in sd a out t f t high t lo w t lo w t r t aa t dh t b uf t su .s t o t su .d a t t hd .d a t t hd .s t a t su .s t a figure 5 -2. write cycle timing scl: serial clock, sda: serial data i/o t wr (1) st op condition st ar t condition w ordn a ck 8th bit s cl s d a note: the write cycle tim e t wr is the time from a valid stop condition of a write sequence to the end of the i nternal clear/write cycle
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 8 figure 5 -3. data validity data change allowed data stable data stable sda scl figure 5 -4. start and stop definitions sd a scl start stop figure 5 -5. output acknowledge st ar t a ckno wledge scl d at a in d at a out 1 8 9
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 9 6. device architecture 6.1 user zones the eeprom user memory is divided into four zones of 256 bits each. multiple zones allow for storage of different types of data or files in different zones. access to user zones is permitted only after meeting proper security requirements. these security requirements are user definable in the configuration memory during device personalization. if the same security requirem ents are selected for multiple zones, then these zones may effectively be accessed as one larger zone. figure 6 -1. user zones zone $0 $1 $2 $3 $4 $5 $6 $7 user 0 $00 - 32 bytes - $18 user 1 $00 - 32 bytes - $18 user 2 $00 - 32 bytes - $18 user 3 $00 - 32 bytes - $18 7. control logic access to the user zones occur only through the control logic built into the device. this logic is configurable thro ugh access registers, key registers and keys programmed into the configuration memory during device personalization. also implemented in the control logic is a cryptographic engine for performing the various higher - level security functions of the device.
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 10 8. configuration memory the configuration memory consists of 2048 bits of eeprom memory used for storage of passwords, keys, codes, and also used for definition of security access rights for the user zones. access rights to the configuration memory are defined in the control logic and are not alterable by the user after completion of personalization. figure 8 -1. configuration memory $0 $1 $2 $3 $4 $5 $6 $7 $00 answer to reset identifitcation $08 fab code mtz card manufacturer code $10 lot history code read on ly $18 dcr identification number nc access control $20 ar0 pr0 ar1 pr1 ar2 pr2 ar3 pr3 $28 reserved $30 $38 $40 issuer code $48 $50 for authentication and encryption use cryptography $58 $60 $68 $70 $78 $80 $88 $90 fo r authentication and encryption use secret $98 $a0 $a8 $b0 pac write 0 pac read 0 password $b8 pac write 1 pac read 1 $c0 pac write 2 pac read 2 $c8 pac write 3 pac read 3 $d0 pac write 4 pac read 4 $d8 pac write 5 pac read 5 $e0 pac w rite 6 pac read 6 $e8 pac write 7 pac read 7 $f0 reserved forbidden $f8
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 11 8.2 security fuses there are three fuses on the device that must be blown during the device personalization process. each fuse locks certain portions of the configuration zone as o tp (one - time programmable) memory. fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. 9. commun ication security modes communications between the device and host operate in three basic modes. standard mode is the default mode for the device after power - up. authentication mode is activated by a successful authentication sequence. encryption mode is ac tivated by a successful encryption activation following a successful authentication. table 9 -1. communication security modes (1) mode configuration data user data passwords data integrity check standard clear clear clear mdc ( 1 ) auth entication clear clear encrypted mac ( 1 ) encryption clear encrypted encrypted mac ( 1 ) note: 1. configuration data include viewable areas of the configuration zone except the passwords: ? mdc ( modi fication detection code ) ? mac ( message authentication code) 10. security options 10.1 anti - tearing in the event of a power loss during a write cycle, the integrity of the device?s stored data is recover able. this function is optional ? t he host may choose to activat e the anti - tearing function, depending on application requirements. when anti - tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data is limited to a maximum of eight bytes for each write re quest. data is written first into a buffer zone in eeprom instead of the intended destination address, but with the same access conditions. the data is then written in the required location. if this second write cycle is interrupted due to a power loss, th e device will automatically recover the data from the system buffer zone at the next power - up. non- volatile buffering of the data is done automatically by the device. during power - up in applications using anti - tearing , the host is required to perform ack p olling in the event that the device needs to carry out the data recovery process. 10.2 write lock if a user zone is configured in the write lock mode, the lowest address byte of an 8 - byte page constitutes a write access byte for the bytes of that page. example: for exam ple, the write lock byte at $080 controls the bytes from $081 to $087. figure 10 -1. write lock example address $0 $1 $2 $3 $4 $5 $6 $7 $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 12 the write - lock byte itself may be locked by writing its least significant (rightmost) bit to ?0?. moreover, when write lock mode is activated, the write lock byte can only be programmed ? that is, bits written to ?0? cannot return to ?1?. in the write lock configuration, wri te operations are limited to writing only one byte at a time. attempts to write more than one byte will result in writing of just the first byte into the device. 10.3 password verification passwords may be used to protect read and/or write access of any user zo ne. when a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or rst becomes active. there are eight password sets that may be used to protect any user zone. only one password is active at a time. presenting the correct write password also grants read access privileges. 10.4 authentication protocol the access to a user zone may be protected by an authentication protocol. any one of four keys may be selected to use with a user zone. authenticatio n success is memorized and active as long as the chip is powered, unless a new authentication is initialized or rst becomes active. if the new authentication request is not validated, the card loses its previous authentication which must be presented again to gain access. only the latest request is memorized. figure 10 -2. password and authentication operations device (card) card number verify a compute challenge b challenge b verify rpw data checksum (cs) verify wpw verify cs write data host (reader) compute challenge a challenge a verify b read password (rpw) verify cs write password (wpw) data cs authentication read access write access note: authentication and password verification may be attempted at any time and in any order. exceeding corresponding authentication or password attempts trial limi t renders subsequent authentication or password verification attempts futile.
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 13 10.5 cryptographic message authentication codes AT88SC0104CA implements a data validity check function in the standard, authentication or encryption modes of operation. in the sta ndard mode, data validity check is done through a modification detection code (mdc), in which the host may read an mdc from the device in order to verify that the data sent was received correctly. in authentication and encryption modes, the data validity c heck becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a message authentication codes (mac). only the host/device that carried out a valid authentication is capable of comp uting a valid mac. while operating in the authentication or encryption modes, the use of mac is required. for an ingoing command, if the device calculates a mac different from the mac transmitted by the host, not only is the command abandoned but the secur ity privilege is revoked. a new authentication and/or encryption activation will be required to reactivate the mac. 10.6 encryption the data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure dat a confidentiality. the issuer may choose to require encryption for a user zone by settings made in the configuration memory. any one of four keys may be selected for use with a user zone. in this case, activation of the encryption mode is required in orde r to read/write data in the zone and only encrypted data will be transmitted. even if not required, the host may still elect to activate encr yption provided the proper keys are known. 10.7 supervisor mode enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. 10.8 modify forbidden no write access is allowed in a user zone protected with this feature at any time. the user zone must be written during devic e personalizat ion prior to blowing the security fuses. 10.9 program only for a user zones protected by this feature, data can only be programmed (bits change from a ?1? to a ?0?), but not erased (bi ts change from a ?0? to a ?1?). 11. protocol selection the AT88SC0104CA supports two different communication protocols. ? smartcard applications: smartcard applications use iso 7816 - b protocol in asynchronous t = 0 mode for compatibility and interoperability with industry standard smartcard readers. ? embedded applications: a two - wire seri al interface provides fast and efficient connectivity with other logic devices or microcontrollers. the power - up sequence determines establishes the communication protocol for use within that power cycle. protocol selection is allowed only during power - up.
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 14 11.1 synchronous two - w ire serial interface the synchronous mode is the default mode after power up. this is due to the presence of an internal pull - up on rst. for embedded applications using cryptomemory in standard plastic packages, this is the only availa ble communication protocol. ? power - up v cc , rst goes high also ? after stable v cc , scl( clk) and sda(i/o) may be driven ? once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device figure 11 -1. synchronous two - w ire protocol v cc i/o-s d a rst clk-scl 1 2 3 4 5 note: five clock pulses must be sent bef ore the first command is issued 11.2 asynchronous t = 0 protocol this power - up sequence complies to iso 7816- 3 for a cold reset in smart card applications. ? v cc goes high; rst, i/o (sda) and clk (scl) are l ow ? set i/o (sda) in receive mode ? prov ide a clock signal to clk (scl) ? rst g oes high after 400 clock cycles the device will respond with a 64 - bit atr code, including historical bytes to indicate the memory density within the cryptomemory family. once asynch ronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. figure 11 -2. asynchronous t = 0 protocol (gemplus patent) v cc i/o-s d a rst clk-scl a tr
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 15 12. initial device programming enabling the security features of cryptomemory requires prior p ersonalization. personalization entails setting up of desired access rights by zones, passwords and key values, programming these values into the configuration memory with verification using simple write and read commands, and then blowing fuses to lock th is information in place. gaining access to the configuration memory requires successful presentation of a secure (or transport) code. the initial signature of the secure (transport) code for the AT88SC0104CA device is $dd 42 97. this is the same as the wri te seven password. the user may elect to change the signature of the secure code anytime after successful presentation. after writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. for additional information on personalizing cryptomemory, please see the application notes programming cryptomemory for embedded applications and initializing cryptomemory for smart card applications from the product page at www.atmel.com/products/securemem .
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 16 13. ordering information atmel ordering code package voltage range temperature range AT88SC0104CA -mj AT88SC0104CA -mp AT88SC0104CA - mjtg AT88SC0104CA - mptg m2 ? j module - is o m2 ? p module - iso m2 ? j module - twi m2 ? p module - twi 2.7v ? 3.6v commercial (0c to 70c) AT88SC0104CA -pu at88sc010 4ca -sh AT88SC0104CA -th AT88SC0104CA - y6h -t 8p3 8s1 8x 8ma2 2.7v ? 3.6v green c ompliant (exceeds rohs)/industrial ( ?40c to 85c) at88sc01 04ca -wi 7 mil wafer 2.7v ? 3.6v industrial ( ?40c to 85c) package type ( 1 ) ( 2 ) m2 ? j module : iso or twi m2 iso 7816 smart card module m2 ? p module : iso or twi m2 iso 7816 smart card module with atmel ? logo 8p3 8- lead, 0.300? wide , plastic dual inline (pdip) 8s1 8- lead, 0.150? wide , plastic gull wing small outline (jedec soic) 8x 8- lead, 4.4mm body , plastic thin shrink small outline (tssop) 8ma2 8- lead, 2.0 x 3.0mm body , 0.50mm pitch , ultra thin mini - map , dual no lead (dfn), (mlp 2x3) note: 1. formal drawings may be obtained from an atmel sales office 2. both the j and p module packages are used for either iso (t=0 / two - wire mode) or twi (two - wire mode o nly)
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 17 14. package information ordering code: mj or mjtg ordering code: mp or mp t g module size : m2 dimension*: 12.6 x 11.4 [mm] glob top: round ? ? 8.5 [mm] thickness: 0.58 [mm] pitch: 14.25 mm module size : m2 dimension*: 12.6 x 11.4 [mm] glob top: squa re ? 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm note: *the module dimensions listed refer to the dimensions of the exposed metal contact area. the actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm great er in both directions (i.e., a punched m 2 module will yield 13.0 x 11.8 mm).
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 18 14.1 ordering code: sh 8s1 ? jedec soic package drawing contact: packagedrawings@atmel.com dra wing no . rev . title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view 8s1 g 6/22/11 notes: this drawing is for general information onl y . refer to jedec drawing ms-012, v ariation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 19 14.2 ordering code: pu 8p3 ? pdip package drawing contact: packagedrawings@atmel.com dr a wing n o . re v . title gpc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, v ariation b a for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0. 1 15 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc e a 0.300 bsc 4 l 0. 1 15 0.130 0.150 2 top view side view end view 8p3 d 06/21/11 8p3, 8-lead, 0.300? wide bod y , plastic dual in-line package (pdip) ptc
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 20 14.3 ordering code: th 8x ? tssop package drawing contact: packagedrawings@atmel.com dr a wing n o . re v . title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. 8x d 6/22/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 21 14.4 ordering code: y6h -t 8ma2 ? ultra thin mini - map title dra wing no. gpc rev . p ac ka g e dr a wing contact: pa c kaged r a wings@atmel.com 8ma2 ynz b 8ma2, 8-pad, 2 x 3 x 0.6 mm bod y , thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbo l min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 1.20 1.30 1.40 a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 ? ? 0.55 c 0.152 ref l 0.30 0.35 0.40 e 0.50 bsc b 0.18 0.25 0.30 3 k 0.20 ? ? 7/15/ 1 1 d2 e2 e e (6x) l (8x) b (8x) pin#1 id a a1 a2 pin 1 id d c k 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5
atmel AT88SC0104CA [ summary datasheet ] 5200fs ? crypto ? 12 /11 22 15. revision histor y doc. rev. date comments 5200fs 12 /2011 update template update package drawings and - replace 8a2 with 8x - replace 8t6 with 8ma2 change AT88SC0104CA -s u to AT88SC0104CA -sh 5200es 08/2009 minor edits and twi module updates 5200ds 07 /2009 minor update s to package drawing information and ordering information 5200cs 05/2009 added mini - map column to table 1- 1 and mini - map pin - out drawing 5200bs 02/2009 connection diagram inserted; dc characteristics table updated 5200as 07/2008 initial document release
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